The present invention relates to a data processor and a data communication method, and more particularly, to a data processor and data communication method for performing data transfer through a direct memory access (DMA) process.
A data processor used in an information device system or the like is typically provided with a direct memory access controller (DMA controller) for reducing the load on its central processing unit (CPU) and improving the data transfer efficiency. When performing data transfer, a CPU cannot execute other calculation processes. However, by employing the direct memory access (DMA) transfer protocol, data transfer does not involve a CPU. Thus, data may be transferred at high speed. In a data processor incorporating such a DMA controller, it is required that data transfer be accurately performed.
FIG. 7 is a block circuit diagram showing a conventional data processor 1, and FIG. 8 is a timing chart thereof. The data processor 1 includes a CPU 2, a memory 3, a transmission DMA controller 4, a reception DMA controller 5, and a binary synchronous serial I/O device (SIO) 6, which are connected to one another by a system bus 7. In the data processor 1, data transfer and exchange of control signals are performed by way of the bus 7.
The data processor 1 includes a clock output terminal SCK, a transmission terminal DOUT, and a reception terminal DIN. In the data processor 1, the SIO 6 is connected to an external device (not shown) via the clock output terminal SCK, the transmission terminal DOUT, and the reception terminal DIN, so that serial data is exchanged with the external device via the terminals SCK, DOUT, and DIN. The circuit configuration of the external device is similar to that of the data processor 1.
The SIO 6, which includes a transmission buffer 8, a reception buffer 9, a transmission shift circuit 10, and a reception shift circuit 11, inputs and outputs data in accordance with the binary synchronous communication protocol. If the transmission buffer 8 is empty, the SIO 6 provides a first activation request signal TRA to the transmission DMA controller 4. If received data Rx (R1, R2, . . . in FIG. 8) is stored in the reception buffer 9, the SIO 6 provides a second activation request signal REC to the reception DMA controller 5. The activation request signals TRA and REC are sent from the SIO 6 to the DMA controllers 4 and 5 via exclusive signal lines L1 and L2, which are separate from the bus 7.
In response to the first activation request signal TRA, the transmission DMA controller 4 issues an occupation request signal DHLD to the CPU 2 to request occupation of the bus 7. After clearing the bus 7, the CPU 2 returns an occupation permission signal DACK to the transmission DMA controller 4 to permit occupation of the bus 7. The occupation request signal DHLD and the occupation permission signal DACK are transmitted via exclusive signal lines L3 and L4, which are separate from the bus 7.
Upon receiving the occupation permission signal DACK, the transmission DMA controller 4 reads transmitted data Tx (T1, T2, . . . in FIG. 8) out of the memory 3 and transfers the transmitted data Tx to the transmission buffer 8 of the SIO 6 via the bus 7. After the transfer, the transmitted data Tx is sent from the transmission buffer 8 to the transmission shift circuit 10. Then, the transmitted data Tx is transmitted from the transmission terminal DOUT in synchronization with a clock signal CLK provided from the clock output terminal SCK.
The SIO 6 receives the received data Rx at the same time as when transmitting the transmitted data Tx. The received data Rx is received by the reception terminal DIN and stored in the reception buffer 9 via the reception shift circuit 11. The received data Rx is stored in the reception buffer 9 when the SIO 6 completes the transmission and reception of data. Thus, the SIO 6 provides a second activation request signal REC to the reception DMA controller 5. In response to the second activation request signal REC, the reception DMA controller 5 issues an occupation request signal DHLD to the CPU 2. After clearing the bus 7, the CPU 2 returns an occupation permission signal DACK to the reception DMA controller 5. Upon receiving the occupation permission signal DACK, the reception DMA controller 5 transfers the received data of the reception buffer 9 to the memory 3.
As described above, the SIO 6 enables high-speed data communication by repeating the transmission and reception operations in accordance with the DMA transfer protocol. Japanese Laid-Open Patent Publication No. 2002-222161 describes a technique for transferring data at high-speeds during direct memory access process in a semiconductor device incorporating a DMA controller.
If transmission is carried out before the received data Rx stored in the reception buffer 9 of the SIO 6 is transferred, overrun will occur in the reception buffer 9. Therefore, to avoid overrun, the data processor 1 must give priority to reception DMA transfer over transmission DMA transfer.
However, some systems to which the data processor 1 is applied must give priority to processing by the CPU 2 over reception DMA transfer. In such systems, even if an occupation request signal DHLD is issued by the reception DMA controller 5 to request occupation of the bus 7, the CPU 2 will not permit occupation of the bus when the CPU 2 is executing processing, which has high priority, and will not output an occupation permission signal DACK. This suspends reception DMA transfer. If the transmission data stored in the transmission buffer 8 of the SIO 6 is transmitted during this suspension, data reception will simultaneously be performed. Thus, overrun will occur in the reception buffer 9.
FIG. 9 is a timing chart showing a case in which overrun occurs. As shown in FIG. 9, after the received data R2 from the reception shift circuit 11 is stored in the reception buffer 9, a second activation request signal REC is output by the SIO 6. In response to the second activation request signal REC, the reception DMA controller 5 issues an occupation request signal DHLD to the CPU 2. In this state, if the CPU 2 is executing processing, which has high priority, the CPU 2 will not permit bus occupation by the reception DMA controller 5. The CPU 2 outputs an occupation permission signal DACK only after completing the processing. Thus, the occupation permission signal DACK is not output during the period the CPU 2 is executing processing. This period defines a reception DMA suspension period X, during which the transfer operation of the received data by the reception DMA controller 5 is suspended.
If transmission data T3 is stored in the transmission buffer 8 in the reception DMA suspension period X, the transmission data T3 is sent to the transmission shift circuit 10 and then transmitted synchronously with a clock signal CLK. In this case, the reception buffer 9, which has already stored the received data R2, will receive the subsequent received data R3 and cause overrun. As a result, the received data R2 which has not yet been read by the reception DMA controller 5 will be destroyed by the subsequent received data R3.
The data processor 1 is provided with a single SIO 6. However, a data processor provided with a plurality of SIOs 6 has also been put to practical use. In the case of such a data processor, the DMA transfer by a certain SIO will be suspended not only when the CPU 2 is executing processing, which has high priority, but also when another SIO is performing data transfer. This increases the possibility of overruns occurring. In other words, if the bus 7 is not cleared for DMA transfer due to other processing than DMA transfer by the SIO 6, it will pose a problem of overrun as shown in FIG. 9.
The occurrence of overrun may be avoided by lowering the priority level of the high priority processing executed by the CPU 2 to a level lower than the priority level of the DMA transfer. However, if the priority level of the processing executed by the CPU 2 is lowered, the CPU 2 will not be able to execute accurate processing precisely and the processing efficiency will be decreased. When a plurality of SIOs 6 are employed, even if priority is given to DMA transfer operations of the SIOs 6, overrun will occur in one of the DMA transfer operations.